About Me

I am a Ph.D. candidate in the Electrical Engineering and Computer Sciences department of the University of California, Berkeley. I am currently on the academic job market seeking a tenure-track assistant professor position. Please feel free to contact me regarding potential opportunities.

I am a computer architecture researcher with broad interests and strong expertise across the full-stack, from chip design and hardware development to system software and application algorithms. Throughout my Ph.D., I addressed interconnected challenges of scalable specialization in domain-specific SoC design cohesively, with rigorous, comprehensive research from concept to silicon validation.

I have published seven architecture papers (five as first author) and in top computer architecture conferences including MICRO, ASPLOS, ISCA, HPCA, and DAC. All of my dissertation work is implemented as a full-stack real-system, evaluated rigorously with FPGA-accelerated RTL simulations, physically validated for feasibility, and fully open-sourced for reproducibility.

I have also led a successful chip tape-out, in which I was in charge of the entire hardware/software design, physical design and testing process.

My work has been recognized with IEEE Micro Top Pick in Computer Architecture (MICRO 2023), the Best Paper Award (DAC 2021), and the Distinguished Artifact Award (ISCA 2023). I am selected as a 2024 Rising Star in EECS by MIT and 2023 ML and Systems Rising Star by MLCommons.

I work in the Berkeley Architecture Research (BAR) group and am affiliated with SLICE (formerly ADEPT) and BWRC, advised by Sophia Shao and Borivoje Nikolić.

Prior to UC Berkeley, I earned B.S. in Electrical and Computer Engineering from Seoul National University.

The best way to reach me is at seah at berkeley dot edu.

Education

University of California, Berkeley
PhD in EECS (from 2019, in progress)

Seoul National University
BS in ECE (2019)